This application claims priority to Japanese Patent Application Number 2001-056114 filed Mar. 1, 2001, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a raised voltage generation circuit used for a semiconductor integrated circuit device. More specifically, the present invention relates to a raised voltage generation circuit used for a nonvolatile semiconductor memory device, and the like, which requires a voltage equal to or higher than a power source voltage, i.e., a raised voltage.
2. Description of the Related Art
In recent years, a power source voltage for a nonvolatile semiconductor memory device (a flash EEPROM) has been decreasing. In general, in order to decrease the power source voltage while maintaining fast access, a selected level of a voltage applied to a word line, which is coupled to a gate of a flash EEPROM cell, is raised to the level of the power source voltage or higher.
In the conventional art, a circuit for generating a raised voltage is well known. FIG. 2 shows a typical raised voltage generation circuit 200. Sources of p-type MOSFETs T8 and T9 are connected to power source voltage Vcc. A gate of the p-type MOSFET T8 and a gate and drain of the p-type MOSFET T9 are connected to a node N7. Thus, the p-type MOSFETs T8 and T9 form a current mirror circuit. The same amount of current flows through each of the p-type MOSFETs T8 and T9. The node N7 is also connected to a drain of an n-type MOSFET T10. Reference voltage Vref is output from a reference voltage generation circuit V1 to a gate of the n-type MOSFET T10. On the other hand, voltage Vdiv is applied to a gate of an n-type MOSFET T11, which is paired with the n-type MOSFET T10. Voltage Vdiv is obtained by dividing raised voltage Vout, which is output from a charge pump circuit P2 to an output node N9, using resistances R3 and R4. A drain of a source-grounded n-type MOSFET T12 is connected to sources of the n-type MOSFETs T10 and T11. The n-type MOSFET T12 performs power down control and source potential control of the n-type MOSFETs T10 and T11. A capacitor C2, which is connected to an output of the charge pump circuit P2, smoothes a raised voltage before it is output from the raised voltage generation circuit 200.
In the circuit described above, when the values of reference voltage Vref and divided voltage Vdiv are the same, the amount of current flowing through each of the n-type MOSFETs T10 and T11 are also the same. Thus, a state of equilibrium is achieved between the n-type MOSFETs T10 and T11. However, for example, when raised voltage Vout, which is output from the charge pump circuit P2 through an output node N9, is decreased, and divided voltage Vdiv becomes lower than reference voltage Vref, an amount of current flowing through the n-type MOSFET T11 is decreased and the potential at a node N8, which connects a drain of the p-type MOSFET T8 and a drain of the n-type MOSFET T11 is increased. As a result, a charge pump circuit enable signal ENB, which is output from an inverter I4 to which the potential at the node N8 is input, goes to a low level, so that the operation of the charge pump circuit P2 is activated. Alternatively, when raised voltage Vout at the node N9 rises, and voltage Vdiv becomes higher than voltage Vref, an amount of current flowing through the n-type MOSFET T11 is increased, and the potential at the node N8 is decreased. As a result, the charge pump circuit enable signal ENB goes to a high level, and the operation of the charge pump circuit P2 is stopped. In other words, the potential of the node N8 is determined by a ratio of the currents flowing through the n-type MOSFETs T10 and T11. The inverter I4 performs operation control of the charge pump circuit P2 in accordance with changes in potential at the node N9 from the state of equilibrium so as to maintain output of the raised voltage Vout to be at an approximately constant potential.
There are various types of circuit arrangements for the reference voltage generation circuit V1 for outputting reference voltage Vref. As an example of the reference voltage generation circuit V1, FIG. 3 shows a reference voltage generation circuit including a pair of flash EEPROM cells (for example, floating-gate-type MOS transistors), which is disclosed in Japanese Laid-Open Publication No. 7-72944. Sources of p-type MOSFETs T13 and T14 are connected to output voltage Vout of a charge pump circuit P3. A gate and drain of the p-type MOSFET T13 and a gate of the p-type MOSFET T14 are connected to a node N12. In this structure, the p-type MOSFETs T13 and T14 together function as a current mirror circuit. The same amount of the current flows through each of the p-type MOSFETs T13 and T14. Drains of the p-type MOSFETs T13 and T14 are respectively connected to drains of n-type MOSFETs T15 and T16. Sources of the n-type MOSFETs T15 and T16 are respectively connected to drains of flash EEPROM cells F3 and F4 which have different amounts of charge stored in their floating gates. The n-type MOSFETs T15 and T16 decrease the voltage at the drains of the flash EEPROM cells F3 and F4 to 1 volt or lower. In this example, the voltage applied to each of the gates of the n-type MOSFETs T15 and T16 is 2Vtn, which is twice as large as a threshold voltage of the n-type MOSFETs T15 and T16. Sources of the flash EEPROM cells F3 and F4 are both connected to the ground potential. Reference voltage Vref, which is output from the reference voltage generation circuit V1, and a divided voltage at node N10, which is obtained by dividing reference voltage Vref using resistances R5 and R6, are respectively applied to gates of the flash EEPROM cells F3 and F4. The amount of charge stored in each of the flash EEPROM cells F3 and F4 is adjusted such that a state of equilibrium is achieved, i.e., the same amount of the current flows through each of the flash EEPROM cells F3 and F4, when output voltage Vref is equal to a predetermined potential.
In such a circuit arrangement, when reference voltage Vref is low, the amount of current which flows through the flash EEPROM cell F4 significantly decreases compared to the amount of current which flows through the flash EEPROM cell F3, and the voltage at the node N11 rises. As a result, the voltage at the gate of the n-type MOSFET T17, whose threshold voltage is lower than that of a typical n-type MOSFET, is increased, and output voltage Vout of the charge pump circuit P3 is supplied to reference voltage Vref. Alternatively, when reference voltage Vref is high, the amount of current flowing through the flash EEPROM cell F4 significantly increases in comparison with the amount of current flowing through the flash EEPROM cell F3, and the potential at the node N11 decreases. Thus, supply of Vout to Vref is interrupted by the n-type MOSFET T17. With such an operation, it is possible to maintain reference voltage Vref to be an approximately constant potential. As described above, the reference voltage generation circuit V1 does not operate with a low voltage, and requires a voltage raised by the charge pump circuit P3 as a power source.
There are various types of circuit arrangements for the charge pump circuit P3. FIG. 4 shows a typical charge pump circuit. N-type MOSFETs T18, T19, and T20 are connected in series. Gates of the n-type MOSFETs T18, T19, and T20 are respectively connected to drains thereof, thereby acting as MOS diodes for preventing a backflow from source to drain. A P-type MOSFET T21 receives the charge pump circuit enable signal ENB and supplies power source voltage Vcc to the n-type MOSFET T18. A capacitor C3 is connected between a node N15 and a node N17. The node N15 is connected to the gate of the n-type MOSFET T19. The node N17 is an output node of an inverter I5 which is driven in response to receiving a clock signal CLK1. On the other hand, a capacitor C4 is connected between a node N18 and a node N16. The node N18 is an output node of an inverter I6 which is driven in response to receiving a clock signal CLK2. The node N16 is connected to the gate of the n-type MOSFET T20.
In such a circuit arrangement, initially, a voltage at the node N15 can be represented as a value obtained by subtracting threshold voltage Vtn of the n-type MOSFET T18 from power source voltage Vcc, i.e., Vccxe2x88x92Vtn. As the clock signal CLK1 changes from Vcc to 0V, a voltage at the node N17 is raised from 0V to Vcc, thereby raising the voltage at the node N15 to 2Vccxe2x88x92Vtn. A voltage at the node N16 can be represented as a value obtained by subtracting threshold voltage Vtn of the n-type MOSFET T19 from the voltage at node N15, i.e., 2Vccxe2x88x922Vtn. By changing the clock signal CLK2 from Vcc to 0V, the voltage at the node N18 is raised from 0V to Vcc, thereby raising the voltage at the node N16 to 3Vccxe2x88x922Vtn. The voltage raising operation is performed as described above. The charge pump circuit P3 is always in operation during the operation of the reference voltage generation circuit V1. Furthermore, output voltage Vout varies in accordance with a variation in power source voltage Vcc. Further still, it is possible to maintain the output voltage of the charge pump circuit to be a constant potential, although an additional reference voltage generation circuit is required.
As described above, the reference voltage generation circuit V1 using a flash EEPROM cell requires the charge pump circuit P3. Furthermore, the raised voltage generation circuit 200 additionally requires the charge pump circuit P2 in order to obtain a raised voltage which is used for raising a word line potential. In other words, the raised voltage generation circuit 200 requires two charge pump circuits. In the raised voltage generation circuit 200, a reference voltage generation circuit is essential for maintaining output voltage Vout to be a constant potential.
According to one aspect of the present invention, there is provided a raised voltage generation circuit, including a charge pump circuit for outputting a first voltage, a voltage dividing circuit for receiving the first voltage and outputting second and third voltages, a first transistor for receiving the second voltage at a gate thereof, a second transistor for receiving the third voltage at a gate thereof, and a control circuit for controlling whether or not to operate the charge pump circuit, wherein currents of the same value flow through in the first and second transistors when the first voltage is equal to a predetermined value, currents of different values flow through the first and second transistors when the first voltage is not equal to the predetermined value, and the control circuit controls whether or not to operate the charge pump circuit based on the currents that flow through the first and second transistors.
In one embodiment of the present invention, the control circuit includes a current mirror circuit.
In one embodiment of the present invention, the first transistor, the second transistor, and the control circuit function as a current mirror-type differential amplifier.
In one embodiment of the present invention, the first voltage and the second voltage have the same value.
In one embodiment of the present invention, the first transistor and the second transistor are floating-gate-type MOS transistors, and the amount of charge stored in a floating gate of the first transistor and in a floating gate of the second transistor are different from each other.
With the above structure of the present invention, in a raised voltage generation circuit for generating a raised voltage by using a charge pump circuit, it is possible to maintain an output voltage to be a predetermined potential without using a reference voltage generation circuit which incorporates another charge pump circuit therein. In a conventional raised voltage generation circuit, it is required to provide at least two charge pump circuits, one for generating a raised voltage and the other for generating a reference voltage. In the raised voltage generation circuit according to the present invention, a raised voltage output from the charge pump circuit is used as both the output voltage and the reference voltage of the raised voltage generation circuit. Thus, a stable raised voltage can be output with only one charge pump circuit. A charge pump circuit is a critical element in determining a chip area because of its structure. Therefore, if one charge pump circuit is used for generating both the output voltage and the reference voltage of the raised voltage generation circuit, i.e., if the number of charge pump circuits is reduced, the chip area can be significantly reduced. Moreover, since a reference voltage generation circuit is not used, a reduction in current consumption, a reduction in chip area, and a reduction in the number of control circuits can be achieved.
Thus, the invention described herein makes possible the advantages of providing a raised voltage generation circuit using a charge pump circuit, in which a raised voltage from the charge pump circuit can be controlled so as to be kept constant without using a reference voltage generation circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.